PM=DISABLED_POR_RESET_, B=BUFFER_DISABLED_POR, MW=8_BIT_POR_RESET_VAL, PB=BLSHIGH, PC=ACTIVE_LOW_CHIP_SELE, P=WRITES_NOT_PROTECTED, EW=EXTENDED_WAIT_DISABL
Configuration for EMC_CS0.
| MW | Memory width. 0 (8_BIT_POR_RESET_VAL): 8 bit (POR reset value). 1 (16_BIT_): 16 bit. 2 (32_BIT_): 32 bit. 3 (RESERVED_): Reserved. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |
| PM | Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally. 0 (DISABLED_POR_RESET_): Disabled (POR reset value). 1 (ASYNCHRONOUS_PAGE_MO): Asynchronous page mode enabled (page length four). |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |
| PC | Chip select polarity. The value of the chip select polarity on power-on reset is 0. 0 (ACTIVE_LOW_CHIP_SELE): Active LOW chip select. 1 (ACTIVE_HIGH_CHIP_SEL): Active HIGH chip select. |
| PB | Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLS3:0 signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLS3:0 bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLS3:0 signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH. 0 (BLSHIGH): For reads all the bits in BLS3:0 are HIGH. For writes the respective active bits in BLS3:0 are LOW (POR reset value). 1 (BLSLOW): For reads the respective active bits in BLS3:0 are LOW. For writes the respective active bits in BLS3:0 are LOW. |
| EW | Extended wait (EW) uses the EMCStaticExtendedWait register to time both the read and write transfers rather than the EMCStaticWaitRd and EMCStaticWaitWr registers. This enables much longer transactions. [1] 0 (EXTENDED_WAIT_DISABL): Extended wait disabled (POR reset value). 1 (EXTENDED_WAIT_ENABLE): Extended wait enabled. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |
| B | Buffer enable [2] 0 (BUFFER_DISABLED_POR): Buffer disabled (POR reset value). 1 (BUFFER_ENABLED_): Buffer enabled. |
| P | Write protect 0 (WRITES_NOT_PROTECTED): Writes not protected (POR reset value). 1 (WRITE_PROTECTED_): Write protected. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |